Cooper Bailey

A hardware accelerator for Graph Neural Network aggregation on ZynqBerry 7010, featuring edge-prefetching, a 7-stage pipeline, and 3x speedup.

• • Engineered a GNN aggregation accelerator on the ZynqBerry 7010 utilizing both FPGA fabric and ARM-based control software
• • Implemented edge-prefetching, a 7-stage pipeline, and data forwarding to transfer the critical path from the data path to the memory path
• • Achieved a 3x speedup compared to traditional CPU execution time when running the aggregation step on the Cora dataset

Tilt-controlled mini golf game with SPI LCD graphics and MPU-6050 motion input, randomized holes via RNG, and millisecond timing with SysTick.

• • Developed a fully playable wrist-controlled mini golf game on the Nucleo-L432KC, integrating MPU-6050 gyroscope input over I2C to map real-time wrist movements to ball physics
• • Created SPI-driven LCD graphics with title screens, animations, scoring, and SysTick-timed gameplay, while using the hardware RNG to generate unique hole and ball locations each round
• • CMSIS Register-level peripherals (SPI, UART, RNG, SysTick)

A 5-stage pipelined LEGv8 processor implemented in SystemVerilog, completed through the Cadence ASIC design flow for a 50 MHz signoff tapeout.

• • Implemented a full 5-stage pipeline LEGv8 processor, complete with forwarding, hazard detection, and branch prediction
• • Completed the IC design flow using Cadence, producing the final GDS files and passing signoff with a frequency of 50 MHz
• • Verified chip functionality through custom program utilizing UART peripheral to print 'Hello World' to the console

Designed and verified a 63-tap FIR filter in SystemVerilog with a pipelined multiply-accumulate datapath, integrated with an ARM Cortex-M0 core on a custom ASIC.

• • Designed and verified a 63-tap FIR filter in SystemVerilog, implementing a pipelined multiply-accumulate datapath with fixed-point coefficients
• • Integrated the FIR filter with an ARM Cortex-M0 core on a custom ASIC
• • Completed the full design flow, including functional validation and GDS generation for tapeout

Real-time ECG heart rate monitoring system on STM32L432 using C and FreeRTOS, implementing a digital signal processing pipeline to compute live BPM.

• • Developed a real-time ECG heart rate monitoring system on an STM32L432 using C and FreeRTOS, implementing 500 Hz signal sampling, multi-task scheduling, UART display output, buzzer feedback, and DAC-based debugging
• • Designed and optimized a digital signal processing pipeline with 60 Hz notch filtering, 5 Hz high-pass filtering, and adaptive thresholding
• • Implemented triangle-template R-peak detection and lockout protection to compute live BPM from ECG signals

A performance-oriented text indexing and search system in C++, implementing custom nested hash tables to process large directories efficiently.

• • Engineered a performance-oriented text indexing and search system in C++, implementing custom hash tables and data structures
• • Processed large text files with predictable latency, memory efficiency, and high throughput
• • Utilized Valgrind to verify memory leak-free execution and profile indexing performance

Robust static CMOS 2-bit magnitude comparator with custom gates, logical-effort sizing, and HSPICE timing verification.

• • Logic derivation, minimization, and custom logic design for Greater, Equal, and Less outputs
• • Optimized custom gates at the transistor level to reduce transistor count and critical delay
• • Worst-case delay analysis across single-bit transitions using HSPICE