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This project implements a full-custom 2-bit magnitude comparator using static CMOS logic, producing Greater (G), Equal (E), and Less (L) outputs. The design prioritizes delay, transistor efficiency, and correctness under worst-case input transitions.
Unlike a standard-cell approach, all logic gates were designed at the transistor level, enabling fine-grained control over topology and sizing.
Logic Derivation
Boolean expressions were derived directly from the truth table and optimized to reduce redundant logic:
- Mutual exclusivity between outputs was enforced (G = 0 and L = 0 implies E = 1)
- Logic was structured to minimize series transistor stacks on critical paths
- Custom compound gates were favored over naïve gate composition where beneficial
Circuit Design
- Static CMOS implementation with custom PDN/PUN networks
- Carefully balanced pull-up and pull-down paths to reduce skew
- Transistor sizing guided by logical effort rather than uniform sizing
- Critical paths identified for each output based on input toggling scenarios
Timing & Verification
- Verified using HSPICE transient simulations
- Worst-case delays measured for all single-bit input transitions
- Separate measurements for hi-to-lo delay, lo-to-hi delay, and average propagation delay
- Design iterated to reduce the longest critical delay while preserving noise margins
Key Takeaways
This project strengthened my understanding of:
- Translating Boolean logic into efficient transistor networks
- Delay optimization using logical effort
- Tradeoffs between transistor count, path depth, and performance
- Verification-driven circuit refinement at the device level
Static CMOS 2-Bit Comparator
Robust static CMOS 2-bit magnitude comparator with custom gates, logical-effort sizing, and HSPICE timing verification.
VLSICMOSHSPICELogical EffortTiming Analysis
Highlights
- Logic derivation + minimization + custom logic design
- Optimized custom gates to reduce transistor count and critical delay
- Worst-case delay analysis across single-bit transitions
This project implements a full-custom 2-bit magnitude comparator using static CMOS logic, producing Greater (G), Equal (E), and Less (L) outputs. The design prioritizes delay, transistor efficiency, and correctness under worst-case input transitions.
Unlike a standard-cell approach, all logic gates were designed at the transistor level, enabling fine-grained control over topology and sizing.
Logic Derivation
Boolean expressions were derived directly from the truth table and optimized to reduce redundant logic:
- Mutual exclusivity between outputs was enforced (G = 0 and L = 0 implies E = 1)
- Logic was structured to minimize series transistor stacks on critical paths
- Custom compound gates were favored over naïve gate composition where beneficial
Circuit Design
- Static CMOS implementation with custom PDN/PUN networks
- Carefully balanced pull-up and pull-down paths to reduce skew
- Transistor sizing guided by logical effort rather than uniform sizing
- Critical paths identified for each output based on input toggling scenarios
Timing & Verification
- Verified using HSPICE transient simulations
- Worst-case delays measured for all single-bit input transitions
- Separate measurements for hi-to-lo delay, lo-to-hi delay, and average propagation delay
- Design iterated to reduce the longest critical delay while preserving noise margins
Key Takeaways
This project strengthened my understanding of:
- Translating Boolean logic into efficient transistor networks
- Delay optimization using logical effort
- Tradeoffs between transistor count, path depth, and performance
- Verification-driven circuit refinement at the device level