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This project implements a full-featured 5-stage pipelined LEGv8 CPU in SystemVerilog, completed through the full Cadence ASIC design flow. The processor architecture includes the five classic RISC pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB), separated by pipeline registers.
By shifting from a single-cycle implementation to a pipelined design, the processor achieves higher throughput and can be clocked at a significantly higher frequency, maximizing instruction concurrency.
Features & Architecture
- **5-Stage Pipeline**: Separate IF, ID, EX, MEM, and WB stages with pipeline registers.
- **Forwarding Unit**: Detects raw data hazards (read-after-write) and forwards data from the EX/MEM or MEM/WB pipeline registers directly to the ALU inputs, eliminating stalls for most register-to-register dependencies.
- **Hazard Detection & Flushing**: Identifies load-use hazards and inserts pipeline stalls (bubbles) by disabling write-enables on the PC and IF/ID registers. Resolves branches in the ID stage to reduce the branch penalty, flushing instructions currently in flight when a branch is taken.
- **IC Design Flow**: Completed synthesis and physical design using Cadence Genus and Innovus, generating final GDSII layouts that passed all signoff checks at a target frequency of 50 MHz.
- **Verification**: Verified logic correctness using custom assembly test programs, including a UART-based console output program that prints "Hello World" to the console.
LEGv8 Processor and Tapeout
A 5-stage pipelined LEGv8 processor implemented in SystemVerilog, completed through the Cadence ASIC design flow for a 50 MHz signoff tapeout.
SystemVerilogCadence InnovusCadence GenusASICVLSI
Key Highlights
- • Implemented a full 5-stage pipeline LEGv8 processor, complete with forwarding, hazard detection, and branch prediction
- • Completed the IC design flow using Cadence, producing the final GDS files and passing signoff with a frequency of 50 MHz
- • Verified chip functionality through custom program utilizing UART peripheral to print 'Hello World' to the console
Project Details
This project implements a full-featured 5-stage pipelined LEGv8 CPU in SystemVerilog, completed through the full Cadence ASIC design flow. The processor architecture includes the five classic RISC pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB), separated by pipeline registers.
By shifting from a single-cycle implementation to a pipelined design, the processor achieves higher throughput and can be clocked at a significantly higher frequency, maximizing instruction concurrency.
Features & Architecture
- **5-Stage Pipeline**: Separate IF, ID, EX, MEM, and WB stages with pipeline registers.
- **Forwarding Unit**: Detects raw data hazards (read-after-write) and forwards data from the EX/MEM or MEM/WB pipeline registers directly to the ALU inputs, eliminating stalls for most register-to-register dependencies.
- **Hazard Detection & Flushing**: Identifies load-use hazards and inserts pipeline stalls (bubbles) by disabling write-enables on the PC and IF/ID registers. Resolves branches in the ID stage to reduce the branch penalty, flushing instructions currently in flight when a branch is taken.
- **IC Design Flow**: Completed synthesis and physical design using Cadence Genus and Innovus, generating final GDSII layouts that passed all signoff checks at a target frequency of 50 MHz.
- **Verification**: Verified logic correctness using custom assembly test programs, including a UART-based console output program that prints "Hello World" to the console.