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This project implements a hardware accelerator for Graph Neural Network (GNN) aggregation on the ZynqBerry 7010 board. It leverages a hardware-software co-design approach, utilizing the FPGA fabric for compute-intensive aggregation steps and ARM-based control software for orchestrating data movement.
Key Features
- **AXI-Mediated Data Movement**: High-bandwidth data transfer between DDR memory and on-chip BRAM.
- **Pipelining & Forwarding**: Designed a 7-stage hardware pipeline with data forwarding and edge-prefetching to optimize throughput.
- **Critical Path Optimization**: Shifted the bottleneck from the execution datapath to the memory access path, maximizing efficiency.
- **Performance**: Achieved a 3x speedup compared to software-only CPU execution on the Cora dataset.
GNN Aggregation Accelerator
A hardware accelerator for Graph Neural Network aggregation on ZynqBerry 7010, featuring edge-prefetching, a 7-stage pipeline, and 3x speedup.
VHDLXilinxFPGAZynqBerryAXIBRAMDDR
Key Highlights
- • Engineered a GNN aggregation accelerator on the ZynqBerry 7010 utilizing both FPGA fabric and ARM-based control software
- • Implemented edge-prefetching, a 7-stage pipeline, and data forwarding to transfer the critical path from the data path to the memory path
- • Achieved a 3x speedup compared to traditional CPU execution time when running the aggregation step on the Cora dataset
Project Details
This project implements a hardware accelerator for Graph Neural Network (GNN) aggregation on the ZynqBerry 7010 board. It leverages a hardware-software co-design approach, utilizing the FPGA fabric for compute-intensive aggregation steps and ARM-based control software for orchestrating data movement.
Key Features
- **AXI-Mediated Data Movement**: High-bandwidth data transfer between DDR memory and on-chip BRAM.
- **Pipelining & Forwarding**: Designed a 7-stage hardware pipeline with data forwarding and edge-prefetching to optimize throughput.
- **Critical Path Optimization**: Shifted the bottleneck from the execution datapath to the memory access path, maximizing efficiency.
- **Performance**: Achieved a 3x speedup compared to software-only CPU execution on the Cora dataset.