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This project focuses on the design, verification, and physical implementation of a 63-tap Finite Impulse Response (FIR) digital filter.
Key features:
- **Pipelined MAC Datapath**: Designed a high-throughput multiply-accumulate unit using fixed-point coefficients for hardware-efficient digital signal processing.
- **System Integration**: Integrated the FIR filter block with an ARM Cortex-M0 processor core on a custom ASIC.
- **ASIC Design Flow**: Completed the full physical design flow using Cadence Genus and Innovus, performing functional validation and generating final GDSII files ready for tapeout.
FIR 63-Tap Filter
Designed and verified a 63-tap FIR filter in SystemVerilog with a pipelined multiply-accumulate datapath, integrated with an ARM Cortex-M0 core on a custom ASIC.
SystemVerilogPythonCadence GenusCadence InnovusASICVLSI
Key Highlights
- • Designed and verified a 63-tap FIR filter in SystemVerilog, implementing a pipelined multiply-accumulate datapath with fixed-point coefficients
- • Integrated the FIR filter with an ARM Cortex-M0 core on a custom ASIC
- • Completed the full design flow, including functional validation and GDS generation for tapeout
Project Details
This project focuses on the design, verification, and physical implementation of a 63-tap Finite Impulse Response (FIR) digital filter.
Key features:
- **Pipelined MAC Datapath**: Designed a high-throughput multiply-accumulate unit using fixed-point coefficients for hardware-efficient digital signal processing.
- **System Integration**: Integrated the FIR filter block with an ARM Cortex-M0 processor core on a custom ASIC.
- **ASIC Design Flow**: Completed the full physical design flow using Cadence Genus and Innovus, performing functional validation and generating final GDSII files ready for tapeout.